Research on Design Method of Low Voltage ESD Protection for Chips based on CMOS Technology

Shuyang Liu

doi:10.54691/52vq1z60

Research on Design Method of Low Voltage ESD Protection for Chips based on CMOS Technology

Shuyang Liu

Frontiers in Science and Engineering, (2023), Vol.3, No.12, pp.29-40

Published: December 22, 2023

DOI: 10.54691/52vq1z60

PDF: Download Full Text PDF

Abstract

As integrated circuit technology continuously evolves towards nanometre scales, the susceptibility of chips to Electrostatic Discharge (ESD) under low voltage conditions has significantly increased, posing greater challenges for ESD protection design. Traditionally, ESD protection strategies have centred on high-voltage applications, employing complex and cumbersome circuits and components to enhance tolerance. However, these methods often underperform in low-voltage CMOS processes due to excessive leakage currents, increased chip area, and an inability to meet the requirements of low power consumption and high integration of devices. This study introduces a novel universal framework for low-voltage ESD protection design methods applicable to various CMOS technology standards. The framework not only compares the merits and demerits of existing mainstream ESD protection devices, ESD testing methodologies, and ESD protection networks, but also introduces an innovative analytical paradigm to holistically consider the interplay among these three facets within low-voltage ESD protection design, thereby offering fresh insights for theoretical and practical research. This universal architecture, while ensuring compatibility, also demonstrates exceptional efficiency, which represents it can be easily and swiftly applicable to different CMOS technology standards.

Keywords: CMOS; ESD; Full Chip ESD Protection.

APA Citation: Shuyang Liu (2023). Research on Design Method of Low Voltage ESD Protection for Chips based on CMOS Technology. Frontiers in Science and Engineering, 3(12), 29-40. https://doi.org/10.54691/52vq1z60

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