An Optimization Method for DC Side Voltage Balance Control of HC-SVG based on Delay Signal Cancellation
Abstract: The integration of NPC high-voltage power units into HC-SVG systems introduces high harmonics in the DC capacitor voltage of the CHB unit and NPC DC bus side capacitor voltage, impacting device compensation performance. This study presents a comprehensive analysis of the DC side capacitor voltages of the CHB and NPC units, identifying and assessing their harmonic components. Subsequently, a filter scheme is devised utilizing the delay-cancellation method based on the triangle vector principle to optimize the DC voltage control of the CHB and NPC units. A simulation platform is constructed to validate the proposed theoretical framework. Results demonstrate that the optimized control strategy markedly enhances the compensation capabilities of HC-SVG systems, leading to a notable reduction in total harmonic distortion in both output voltage and compensation current under identical operational conditions, thereby enhancing the compensation performance of HC-SVG systems.
References
- Du Shaotong, Liu Jie, Zhou Juan, et al. A 6kV Static Var Generator Based on NPC and H Bridge Hybrid Cascade [J].2021-10-14.
- Du Shaotong, Tan Xingguo, Zhou Juan. Capacitance value analysis and DC voltage control of H-bridge cascade STATCOM with reduced capacitance [J]. Power Grid Technology, 2019, 43 (1): 275 - 284.
- Nan Yannan, Lu Xiangdong. Research on SVG power reactive power compensation based on filter lifting [J]. Grid and Clean Energy, 2018, 34 (5): 31-35.
- Liu Y ,Guo Z ,Liu F , et al.A Real-Time Diagnosis Method of Open-Circuit Faults in Cascaded H-Bridge RectifiersBasedonVoltage Threshold and Current Coefficient of Variation[J].Electronics,2025,14(5):986-986.
- Li Xinian, Xu Tao, Niu Decun. Fast Delay Signal Cancellation Filtering Method Based on Vector Triangle Principle [J]. Journal of China Electrical Engineering, December 5, 2021.
- Yang Shaobo, Zeng Siming, Zhou Wen, et al. Delay signal phase lock cancellation technology and analysis of delay error effect [J]. Power Electronics Technology, 2021, 55(09): 31-35+47.